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Chapitre D'ouvrage Année : 2021

Removing Load/Store Helpers in Dynamic Binary Translation

Olivier Gruber
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Frédéric Pétrot

Résumé

During dynamic binary translation (DBT), guest memory accesses need to be translated from guest virtual memory addresses to virtual host memory addresses, a translation that is time-consuming and greatly impacts the performance of the overall emulation. In this chapter, the authors propose translating a guest load/store instruction into a host load/store instruction, leveraging the host memory management unit (MMU) to perform the address translation at native speed. This requires that the emulator maps the guest virtual address space in a region of its own address space, using a Linux kernel module to control the host MMU translation in that region. The authors give an overview on what is necessary, in a DBT-based emulator, to emulate memory accesses. They describe their prototype based on Linux and QEMU, on x86_64 processors for the host.
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Dates et versions

hal-03245419 , version 1 (01-06-2021)

Licence

Paternité - Pas d'utilisation commerciale

Identifiants

Citer

Antoine Faravelon, Olivier Gruber, Frédéric Pétrot. Removing Load/Store Helpers in Dynamic Binary Translation. Multi‐Processor System‐on‐Chip, iste - international scientific and technical encyclopedia, pp.133-160, 2021, 9781789450217. ⟨10.1002/9781119818298.ch7⟩. ⟨hal-03245419⟩
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